Logic Gates

1. Objective:

Design, Simulate and Implement Inverter, NAND, NOR gate using MOSFETS.

2. Brief description of the theory

CMOS also known as Complementary symmetry metal oxide semiconductor consists of a symmetrical pairs P-type and N-type MOSFET transistors. These transistor as used for the logic functions in the circuit. These P-type and N-type are always in the pairs for maximum optimization. The most common design in CMOS transistor are NMOS connected to the bottomof PMOS. These PMOS and NMOS are connected in opposite way. Whenever the P-type are in series the N-type are in parallel and vice versa. So, the combination of these two transistors are used to make a logic gates and are used for the digital circuits. Here, in the CMOS transistors, the PMOS transistor acts as an open switch whenever the input voltage is high or the logic 1 while NMOS acts as a closed switch and vice versa with the input. Because of such property of PMOS and NMOS the CMOS transistor are used to build logic gates. Moreover, these transistor acts as a switch and its property is shown in the table 1.

Table 1: MOSFET transistor as a switch

Logic	PMOS	NMOS
0	Acts as closed switch	Acts as open switch
1	Acts as open switch	Acts as closed switch

Inverter

Using such property we can build the desired logic gates. For example, an inverter can be built simply combining PMOS in series with NMOS as shown in the figure 1 where the drain of both PMOS and NMOS are connected together and the output is taken from the drain of either PMOS or NMOS. The VDD is connected to PMOS whereas the ground is connected to NMOS transistor. The truth table for Inverter or NOT gate are as follow

Table 2: Inverter/NOT gate Truth Table

Input	Output
0	1
1	0

Schematics

NAND Gate:

The simple definition of NAND gate is not AND or inverted AND. The NAND gate can be also constructed using 2 PMOS and 2 NMOS transistors. In this case the PMOS are connected parallel to each other where they have a common VDD and the NMOS are connected in series with the drain of PMOS. Output is collected is the drain of either transistor and the NMOS is grounded. The truth table of NAND are shown in table 3.

Table 3: NAND Gate Truth Table

Input	Input	Output
0	0	1
0	1	0
1	0	0
1	1	0

Schematics

NOR Gate :

The simple definition of NOR gate is not OR or inverted OR. The NAND gate can be also constructed using 2 PMOS and 2 NMOS transistors where the PMOS are now connected in series and the NMOS are connected in parallel with the drain of bottom PMOS as shown in the figure 5. These NMOS have the common ground or VSS. The output is collected is the drain of either transistor where the PMOS and NMOS transistors are connected. The input is given from the Gate which would make the NOR show these property as shown in table 4 and the NMOS is grounded. The truth table of NAND are shown in table 4

Table 4: Truth Table for NOR Gate

Input	Input	Output
0	0	1
0	1	1
1	0	1
1	1	0

Schematics